1. Field of the Invention
The present invention relates to analog to digital converters ADC, and more particularly, to analog to digital converters utilizing track-and-hold amplifiers for high speed operation.
2. Related Art
A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC""s (i.e. high speed, low power, low area, high resolution). FIG. 1 shows the generic two-step subranging architecture, comprising a reference ladder 104, a coarse ADC 102, a switching matrix 103, a fine ADC 105, coarse comparators (latches) 107, fine comparators (latches) 108 and an encoder 106. In most cases, a track-and-hold 101 is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC 102. The coarse ADC 102 and the coarse comparators 107 compare the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix 103 connects the fine ADC 105 and the fine comparators 108 to a subset of the reference voltages (called a xe2x80x9csubrangexe2x80x9d) that is centered around the input signal voltage. The coarse and fine comparators 107, 108 latch the outputs of the coarse and fine ADC""s 102, 105 prior to inputting them to the encoder 106.
High-speed high-resolution ADC""s usually use a track-and-hold (T/H) or a sample-and-hold (S/H) preceding the ADC. The main distinction between a S/H and a T/H is that a S/H holds the sampled input signal for (almost) a full clock period, whereas a T/H holds the sampled input signal for (almost) half a clock period.
In general, a S/H requires more area and power than a T/H to obtain the same performance. However, the disadvantage of a T/H is that the sampled input signal is available to the ADC for only half a clock period.
Other subranging ADC""s are known that can use a T/H instead of a S/H. However, the timing proposed in conventional art has important disadvantages.
Typically, both the coarse and fine ADC amplifiers reset to the T/H output voltage. This leaves much less time available for the coarse ADC amplifiers to amplify the signals and the coarse comparators to decide on a voltage to latch. This will impact a maximum sampling speed Fsample that the ADC can run at.
Some ADC""s use a T/H, where the same physical circuits are used for performing both the coarse and the fine quantization. This leaves only xc2xc of a clock cycle available for performing the coarse quantization, or two time-interleaved sub-ADC""s have to be used. This impacts either maximum possible operating speed, or doubles required area and power.
Thus, one of the bottlenecks in subranging ADC""s is the limited amount of time available for performing the coarse quantization. Several different timing methods for subranging ADC""s are known for optimizing this bottleneck. Unfortunately, most of these solutions require the use of a S/H, or use time-interleaved ADC""s. This disadvantageously affects the required power and area.
The present invention is directed to an analog to digital converter that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided an N-bit analog to digital converter including a reference ladder, a track-and-hold amplifier connected to an input voltage, and a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock. A fine ADC amplifier connected to a fine capacitor at its input and has a fine ADC reset switch controlled by a second clock phase of the two-phase clock. A switch matrix selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier. The coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output voltage during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output voltage during the second clock phase. An encoder converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
In another aspect of the present invention there is provided an N-bit analog to digital converter including a reference ladder, a track-and-hold amplifier tracking an input voltage, a two-phase clock having phases xcfx861 and xcfx862, and a plurality of coarse ADC amplifiers each connected to a corresponding coarse capacitor at its input. The coarse ADC amplifiers are reset on xcfx861 and their corresponding coarse capacitors are connected to the T/H output voltage on xcfx862. A plurality of fine ADC amplifiers are each connected to a corresponding fine capacitor at their input. The fine ADC amplifiers are reset on xcfx862 and their corresponding fine capacitors are charged to the T/H output voltage on xcfx862. A switch matrix selects a voltage subrange from the reference ladder based on outputs of the coarse ADC amplifiers for input to the fine ADC amplifiers on xcfx861. An encoder converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
In another aspect of the present invention there is provided a N-bit analog to digital converter including a reference ladder, a track-and-hold amplifier tracking an input voltage, a two-phase clock having phases xcfx861 and xcfx862, a coarse capacitor connected to the track-and-hold amplifier on xcfx862 and to the reference ladder on xcfx861, a coarse ADC amplifier that resets on xcfx861 and amplifies a voltage on the coarse capacitor on xcfx862, and a coarse comparator for latching an output of the coarse ADC amplifier on xcfx861+1 cycle. A fine capacitor is connected to the track-and-hold on xcfx862 and to a fine voltage tap of the reference ladder on xcfx861, the fine voltage tap selected based on the output of the coarse ADC amplifier. A fine ADC amplifier includes a plurality of cascaded amplifier stages. A first cascaded amplifier stage resets on xcfx862 and amplifies a voltage on the fine capacitor on xcfx861+1 cycle, a second cascaded amplifier stage resets on xcfx861+1 cycle and amplifies the voltage on the fine capacitor on xcfx862+1 cycle, a third cascaded amplifier stage resets on xcfx862+1 cycle and amplifies the voltage on the fine capacitor on xcfx861+2 cycles, and so on. A fine comparator latches an output of a last cascaded amplifier stage on xcfx861+3 cycles, and an encoder converts outputs of the coarse and fine comparators to an N-bit output.
In another aspect of the present invention there is provided an N-bit analog to digital converter including a reference ladder, a track-and-hold amplifier tracking an input voltage, a two-phase clock having alternating phases xcfx861 and xcfx862, a plurality of coarse capacitors connected to an output of the track-and-hold on xcfx862 and to corresponding coarse taps of the reference ladder on xcfx861, and a plurality of coarse ADC amplifiers that reset on xcfx861 and amplify voltages on the coarse capacitors on xcfx862. A plurality of coarse comparators latches outputs of the coarse ADC amplifiers. A plurality of fine capacitors connected to the output of track-and-hold amplifier on xcfx862 and connected to fine voltage taps of the reference ladder on xcfx861, the fine voltage taps are selected based on the outputs of the coarse ADC amplifiers. A plurality of fine ADC amplifiers, each including a plurality of cascaded amplifier stages. The cascaded amplifier stages reset and amplify on alternating phases xcfx861 and xcfx862, wherein amplifiers of the first stage are reset on xcfx862 and amplify voltages of the fine capacitors on xcfx861, a plurality of fine comparators for latching outputs of a last amplifier stage. An encoder converts outputs of the coarse and fine comparators to an N-bit output.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.